GMS30C7201 Datasheet, PDF (173/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Baud Rate Divisor (BRD)
The 1-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the MIr. Two
different baud rates can be selected:0.576Mbit/s and 1.152Mbit/s. The baud rate generator uses
the 48MHz clock generated by the on-chip PLL, divided down to the current data rate as defined
by the BRD bit. The receive baud clock is synchronized with the data steam each time a positive
edge transition is detected on the receive data line.
Thus:
• when BRD=0, MIr operates at 0.576Mbit/s
• when BRD=1, MIr operates at 1.152Mbit/s
This bit has no effect when the FIr is selected.
Transmit buffer Underrun Select (TUS)
The transmit buffer underrun select (TUS) bit is used both to select what action to take as a result
of a transmit buffer underrun, as well as mask or enable the transmit buffer underrun interrupt.
When TUS=0, transmit buffer underruns are used to signal the transmit logic that the end of the
frame has been reached. When the transmit buffer experiences an underrun, the CRC value
which is calculated continuously on outgoing data is loaded to the serial shifter and transmitted,
followed by the stop flag and SIP pulse. Also when TUS=0, the transmit buffer interrupt is
masked and the state of the transmit buffer underrun (TUR) status bit is ignored by the interrupt
controller.
When TUS=1, transmit buffer underruns are used to signal the transmit logic that the end of the
frame has not yet been reached and that the rate in which data is supplied to the transmit buffer
is not sufficient. When the transmit buffer experiences an underrun zeroes are continuously
output by the transmitter to signal an abort condition until data is once again available within
the transmit buffer, and the CRC value is discarded. Additionally, when TUS=1, the transmit
buffer underrun interrupt is enabled, and whenever TUR is set (one) an interrupt request is made
to the interrupt controller. To change the state of this bit during operation, the user should fill
the transmit buffer to ensure TUS is not written at the same time the transmit buffer underruns.
Note that programming TUS=0 does not affect the current state of TUR or the transmit buffer
logic’s ability to set and clear TUR, it only blocks the generation of the interrupt request.
TUS is useful for ensuring that frames are not prematurely ended due to an unexpected transmit
buffer underrun. At the start of a frame the user may configure TUS=1 such that any underrun
signals an abort to the off-chip receiver. Just before the end of the frame the user may then
configure TUS=0, allowing the remaining data to be output by the transmit logic. The buffer
then underruns, causing the CRC, stop flag, and SIP to be transmitted.
Transmit Enable (TXE)
The transmit enable (TXE) bit is used to enable and disable the MIr/FIr transmit sub-module
selected using the IrEnable register. When TXE=0, the transmit logic is disabled and its clocks
are turned off to conserve power. When TXE=1, the transmitter logic is enabled for IrDA
transmission. It is required that the user first program all other control bits before setting TXE.
If the TXE bit is cleared to zero while the is actively transmitting data, transmission is stopped
immediately, all data within the transmit buffer and serial output shifter is cleared. Clearing
TXE to zero ensures the transmitter is disabled. Note that TXE is ignored by the SIr (which is
always enabled whenever selected by the IrEnable register).
Also note that even though the IrDA standard only permits half-duplex operation, this
implementation does not restrict the user from transmitting and receiving data at the same time;
both are fully independent units. This function is particularly useful when using loop back
mode, described above.
GMS30C7201 Data Sheet
12-19