GMS30C7201 Datasheet, PDF (277/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
The timing and control block produces all necessary control signals of the SPI-MMC block
including SPICLK. The frequency of SPICLK signal is programmable.
SPI-MMC transfer’s protocol is command and response. Whenever CP sends a command to
MMC (via SPI), MMC sends CP (via SPI) a response. The response is variable length for
command—for example, there is 1-, 6-, 17-byte. There is only 6 byte in command.
Consider the sequence of operations that occur in a read transfer.
1 CP send a reset signal to the SPI-MMC block. In other word, CP write “0” to bit in the
ResetReg register. The signal is used to clear counters inside the block.Before new
exchange begins and the content of XCHCOUNTER is changed, and transmit mode is
changed (XCHMODE BIT in the SPICR), CP must send a reset signal to the SPI-
MMC block.
2 First, CP set up the SPICR register. In this example, XCHMODE is send mode.
3 CP write number to send into XCHCOUNTER register.
4 CP write “Data read command(CMD17)” into the TX FIFO.
5 CP asserts CS signal. In other words, CP write 0 to CS bit in the SPICR.
6 CP send a start signal to SPI-MMC. In other word, CP set XCH bit in the SPICR.
7 The SPI-MMC block sends out 6 byte of command data from TX FIFO through TX
shift register.
8 The SPI-MMC block issues the interrupt after it send all data in TX FIFO.
9 The CP reads the SPISR register in The SPI-MMC block and disable start signal (reset
XCH bit). In other words, CP writes the SPICR register.
10 CP send a reset signal to the SPI-MMC block. In other word, CP write 0 to bit in the
ResetReg register. The signal is used to clear counters inside the block. Before new
exchange begins and the content of XCHCOUNTER is changed, and transmit mode is
changed (XCHMODE BIT in the SPICR), CP must send a reset signal to the SPI-
MMC block.
11 CP changes transmit mode.(XCHMODE is receive mode)
12 The CP write number to be received into XCHCOUNTER register.
13 CP send a start signal to SPI-MMC (set XCH bit).
14 Then SPI-MMC block receives response from MMC.
15 After SPI-MMC receives 1 byte (for CMD17 command), it sets XCH DONE status
bits and it issues interrupt to a CP.
16 The CP reads the SPISR register in the SPI-MMC block and disable start signal (reset
XCH bit). In other words, CP writes the SPICR register.
17 The CP read data RX fifo.
18 After CP takes this response data and examine it, CP act as response data.If there is no
error indication in response, CP informs SPI-MMC block that MMC sends data to it.
19 CP sends a reset signal to the SPI-MMC block. In other words, CP write 0 to bit in the
Reset register. The signal is used to clear counters inside the block. Before new
exchange begins and the content of XCHCOUNTER is changed, and transmit mode is
changed (XCHMODE BIT in the SPICR), CP must send a reset signal to the SPI-
MMC block.
20 The CP write number to be received into XCHCOUNTER register.
21 CP send a start signal to SPI-MMC (set XCH bit).
22 The SPI-MMC block receives data from MMC (for example, data length is from 4 byte
to 515 byte.)
23 If SPI-MMC receives data like RX FIFO size, SPI-MMC block sets the “RX FIFO
full” status bit and issues an interrupt to CP.At this time SPICLK disable start signal
for prevention of RX FIFO overrun.If CP takes all data in RX FIFO, CP sends a start
signal a and receives response to remain. Repeat it.
24 After SPI-MMC block receive all data from MMC, it sets the XCH DONE status bit
and issues an interrupt to CP.
GMS30C7201 Data Sheet
13-49