GMS30C7201 Datasheet, PDF (276/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Name
BnRES
SPIIRQ
PCLK
Description
Reset signal (active LOW)
This signal goes to HIGH if this interrupt is enabled and if either
the TX or RX operation is completed.
This input clock signal has the frequency of 3.6864MHz
Table 13-34: Signal description (Continued)
The SPI-MMC has four signals connected to the external MMC:
• CS - Chip select signal for external MMC
• SPICLK - Serial clock signal to the external MMC
• MOSI - Serial data output signal to the external MMC
• MISO - Serial data in signal from the external MMC
13.8.2 Overall structure and operation
A block diagram of the SPI-MMC is shown in Figure 13-5: SPI-MMC block diagram
overview.
CP(APB)
PCLK
Tx data buffer
Rx data buffer
Tx shift register
Rx shift register
MOSI
MISO
Timing & control
block
counters
SPICLK
CS
13-48
Figure 13-5: SPI-MMC block diagram overview
The TX FIFO and RX FIFO in Figure 13-5: SPI-MMC block diagram overview are FIFO
buffers. In the current design, it is assumed that each buffer contains eight entries, where each
entry is 8-bit wide.
After CP writes a sequence of data to the TX FIFO, the content of the FIFO is loaded into the
TX shift register and is shifted out serially one byte at a time. When all elements in the TX FIFO
are transferred to the TX shift register, the SPI-MMC issues an interrupt to CP, which may fill
the TX FIFO for further data transfer.
Serial input data is shifted into the RX shift register. After 8 bits are shifted in, the content of
the RX shift register is copied into the RX FIFO. When the RX FIFO is full, the SPI-MMC
issues an interrupt to CP through the SPIIRQ signal. CP reads the content of the RX FIFO in an
interrupt service routine.
GMS30C7201 Data Sheet