GMS30C7201 Datasheet, PDF (219/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
TicREG (The input TIC register for TIC mode) (Base address+0x18)
Bit 7
6
5
4
3
2
1
0
RESERVED
TICvmin TICvpin TICrcvin
Figure 12-28: Input TIC register for TIC mode
TICvmin, TICvpin, TICrcvin: this value is set to the TIC vector by TIC. These bits are set based
on the 48MHz clock signal generated by TIC.
TicRESULT (The output TIC register for TIC mode) (Base address+0x1c)
Bit
7
6
5
4
3
2
1
0
RESERVED
TICusboen TICvmo TICvpo
Figure 12-29: Output TIC Register for TIC mode
TICusboen, TICvmo, TICvpo: the values of these bits are compared with the TIC vector by TIC,
based on the 48MHz clock signal generated by TIC.
CONTswreset (generate software reset to USBD) (Base address+0x20)
Bit
7
6
5
4
3
2
1
0
RESERVED
ESWRES
Figure 12-30: Generate software reset to USBD
ESWRES: this bit should be set to ‘1’ after PMU generated 48 Mhz USBD clock. If this bit is
‘1’, the dpll (digital pll) in the USBD is initialized and so USBD operates successfully. After
data transfer has finished, the bit should be set to ‘0’.
CONTdrqmask (USBD DMAC request masking register) (Base address+0x24)
GMS30C7201 Data Sheet
12-65