GMS30C7201 Datasheet, PDF (158/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.2.2 Block Diagram
DMAREQ[2:0]
Chan[1:0]
DMA
operation
register
block
Register
select
TransendINT
Channel
control
register
Address count
(Sound I/O)
Address count
(ICP I/O)
Address count
(USB I/O)
Transfer count
(Sound I/O)
Transfer count
(ICP I/O)
Transfer count
(USB I/O)
BUS IF
ASB BUS
Figure 12-1: DMAC Block Diagram
12.2.3 Signal Description
The DMAC module is connected to the ASB.
Name
BCLK
BnRES
BA[31:0]
12-4
Type
In
Source/
Destination
Clock controller
In
InOut
Reset Controller
ASB bus
Description
System (bus) clock. This clock times all bus transfers. The clock has
two distinct phases - phase 1 in which BCLK is LOW, and phase 2 in
which BCLK is HIGH.
These signals indicate the reset status of the bus
ASB address. Output for DMAC operation.Input for Register access.
Table 12-1: ASB Signal Description
GMS30C7201 Data Sheet