GMS30C7201 Datasheet, PDF (33/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

3.1.2 ASB
3.1.3 Video bus
3.1.4 APBs
Architecture Overview
The ASB is designed to allow the ARM to have continuous access to both the ROM/PCMCIA
interface and the SDRAM. The SDRAM controller straddles both the ASB and the video DMA
bus so the LCD and VGA can access the SDRAM controller simultaneously with activity on the
ASB. This means that the ARM or Piccolo can read code from ROM, or access a peripheral,
without being interrupted by video DMA.
The GMS30C7201 uses a modified arbiter to control mastership on the main ASB bus. The
arbiter only arbitrates on quad-word boundaries, or when the bus is idle. This is to get the best
performance with the ARM720T, which uses a quad-word cache line, and also to get the best
performance from the SDRAM, which uses a burst size of eight halfwords per access. By
arbitrating only when the bus is idle or on quad-word boundaries (A[3:2] = 11), it ensures that
cache line fills are not broken up, hence SDRAM bursts are not broken up.
Video ASB arbitration is controlled by the SDRAM controller. This is explained in 3.2.2
Arbitration on page 3-4.
The video bus hosts the LCD controller and the VGA controller DMA. The video bus consists
of separate address inputs, a request / acknowledge to / from the SDRAM controller, for each
of the LCD and VGA blocks, and a shared data bus. The LCD and VGA registers are
programmed from the fast APB. The SDRAM controller arbitrates between ASB, VGA and
LCD access requests. Video always has higher priority than ASB access requests. The split
ASB/video bus architecture of the SDRAM controller allows slow device accesses—such as
access to a PC-Card that asserts a WAIT signal for several microseconds—without blocking
video DMA.
There are two APB buses. These are the fast and slow APB buses. The fast APB bus operates
at the speed of the ASB (30 MHz), and hosts the Fast and Medium speed infra-red interface, the
USB interface, the sound output interface, and the LCD and VGA registers. These are the high
performance peripherals, which are generally DMA targets.
The slow APB peripherals generally operate at the UART crystal clock frequency of
3.6864MHz, though register access via the APB is at ASB speed. The slow APB peripherals do
not support DMA transfers. This arrangement of operating most of the peripherals from a slower
clock, and reducing the load on the faster bus, results in significantly reduced power
consumption. Both APB buses connect to the main ASB bus via specially modified bridges.The
slow APB bridge takes care of all re-synchronization, handing over data and control signals
between the ASB and UART clock domains in a safe and reliable manner.
The fast APB bridge is modified from the normal AMBA bridge, to allow DMA access to fast
APB peripherals. Additional signals from the DMA controller to the APB bridge request, select
and acknowledge DMA transfers to and from DMA-aware peripherals.
GMS30C7201 Data Sheet
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