GMS30C7201 Datasheet, PDF (141/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.6.6 Invert Pixel Clock (IPC)
The Invert Pixel Clock (IPC) bit is used to select which edge of the pixel clock pixel data is
driven out onto the LCD’s data lines. When IPC=0, data is driven onto the LCD’s data lines on
the rising-edge of LcdCP. When IPC=1, data is driven onto the LCD’s data lines on the falling-
edge of LcdCP.
11.6.7 Invert Output Enable (IEO)
The Invert Output Enable (IEO) bit is used to select the active and inactive state of the output
enable signal in active display mode. In this mode, the AC-bias pin is used as an enable that
signals the off-chip device when data is actively being driven out using the pixel clock. When
IEO=0, the LcdAC pin is active HIGH. When IEO=1, the LcdAC pin is active LOW. In active
display mode, data is driven onto the LCD’s data lines on the programmed edge of LcdCP when
LcdAC is in its active state.
Bit
4-0
5
10-6
11
12
13
14
15
25-16
26
Name
PCD
PCS
ACB
IVS
IHS
IPC
IEO
SLV
CPL
BCD
Description
Pixel Clock Divisor
Used to specify the frequency of the pixel clock based on the LCD clock (LcdCLK) frequency.
Pixel clock frequency can range from LcdCLK/2 to LcdCLK/33.
Pixel Clock Frequency = LcdCLK/(PCD+2).
Pixel Clock Source
0 - Video DMA bus clock
1 - VGA clock
AC Bias Pin Frequency
Number of line clocks to count before toggling the AC Bias pin. This pin is used to periodically
invert the polarity of the power supply to prevent DC charge build-up within the display.
Program to value required minus 1.
Invert VSync
0 - LcdFP pin is active HIGH and inactive LOW.
1 - LcdFP pin is active LOW and inactive HIGH.
Invert Hsync
0 - LcdLP pin is active HIGH and inactive LOW.
1 - LcdLP pin is active LOW and inactive HIGH.
Invert Pixel Clock
0 - Data is driven on the LCD’s data lines on the rising-edge of LcdCP.
1 - Data is driven on the LCD’s data lines on the falling-edge of LcdCP.
Invert Output Enable
0 - LcdAC pin is active HIGH in TFT mode
1 - LcdAC pin is active LOW in TFT mode.
Slave mode
Slave (or genlock) LCD to VGA video. The HSync and VSync are locked to the VGA timing
generator. The LCD horizontal timing must be carefully programmed if sharing DMA data
Clocks Per Line
This field specifies the number of actual clocks to the LCD panel on each line. This the number
of pixels per line divided by either 1 (TFT), 4 or 8 (for mono passive), 2²/₃ (for color passive),
minus one.
Bypass Pixel Clock Divider
Table 11-5: LCD Controller Bit Fields
GMS30C7201 Data Sheet
11-13