GMS30C7201 Datasheet, PDF (65/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Piccolo Enable Register
PMU & PLL
Bit
Name
Function
0
PICENABLE Enable Piccolo coprocessor
Table 7-3: Piccolo Enable Register
Piccolo is enabled when ARM 7201 comes out of reset. Software should disable the Piccolo as
soon as possible in the reset sequence to conserve power by writing a 0 to this location.
Subsequently, software should only enable Piccolo when running an application that requires
Piccolo (such as Soft Modem).
ID register
This read-only register returns a unique chip revision ID. Revision 0 of the GMS30C7201
device (the first revision), will return the constant value 0x00720100.
Bus Retract register
Bit
Name
Function
0
BRDelay
0: bus retracts after 8 cycles
1: bus retracts after 12 cycles
1
BRENABLE Enables bus retracts
Table 7-4: Bus Retract Register
BRENABLE enables correct DMA operation when slow peripherals are connected to the
external bus. When enabled, bus retracts occur when either nPCAWAIT, nPCBWAIT or
EXPRDY are held active by a slow external peripheral for more than the number of clocks
specified by BRDelay. The bus retract ensures the DMA is not stalled for the duration of the
slow peripheral bus access
Reset / Status register
This read/write register provides status information on power on reset and the PLL status. The
allocation is a shown in Table 7-6: ResetStatus Register Bits. The bits in this register are
‘sticky’ bits. For a definition of a sticky bit please refer to Wake-up Debounce and Interrupt
on page 7-7. Generally, this register will be read each time the ARM exits reset mode, so that
the ARM can identify what event has caused it to exit from reset mode.
ResetStatus register
READ bits
0
1
2
3
4
5
GMS30C7201 Data Sheet
Register bit meaning
PORStatus
PLLLock1
PLLLock2
PLLLock3
OnEvt (debounced)
RIEvt (debounced)
Table 7-5: Table Reset and PLL Status Register
7-9