GMS30C7201 Datasheet, PDF (287/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
SCLK
SDFS
DATA
CONTROL
MSB MSB-1
15
14
C1
C0
LSB
0
XPD R
Figure 13-9: CODEC protocol diagram
Interrupts
The AFE Interface has three interrupt sources that assert an active HIGH interrupt. These
interrupts are unmasked by setting the enable bits in the CR to 1.
Interrupt Source
TXFEI
RINGI
FIFOERRORI
Issuance Condition
Transmit-FIFO empty
RING input is HIGH
FIFO Error (no data to send)
Method to clear Interrupt
After read SR
After read SR
After read SR
Table 13-40: Interrupt sources
13.9.4 Programmer’s Model
AFE registers
The following user registers are provided:
• Transmit Data Register (TXDR)
• Receive Data Register (RXDR)
• Reference Value Register (RVR)
• Control Register (CR)
• Status Register (SR)
TXDR (Transmit Data Register) is a 32-bit write-only register, in which transmit data is stored.
Writes to this register will push the data into the transmit FIFO. All the bits in this register are
initialized to 0 at reset.
Bit
Name
31:0
data
Function
Transmit data
Table 13-41: TXDR bit functions
GMS30C7201 Data Sheet
13-59