GMS30C7201 Datasheet, PDF (245/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
activating the INTUART output signal. All other system functions operate in their normal
manner, including the setting of the Line Status and MODEM Status Registers. Table 13-6:
Summary of registers on page 13-10 shows the contents of the IER. Details on each bit follow.
Bit 0:
This bit enables the Received Data Available Interrupt (and time-out
interrupts in the FIFO mode) when set to logic 1.
Bit 1:
This bit enables the Transmitter Holding Register Empty Interrupt when set
to logic 1.
Bit 2:
This bit enables the Receiver Line Status Interrupt when set to logic 1.
Bit 3:
This bit enables the MODEM Status Interrupt when set to logic 1.
Bit 4–7: These four bits are always logic 0.
MODEM Control Register
This register controls the interface with the MODEM or data set (or a peripheral device
emulating a MODEM). The contents of the MODEM Control Register are indicated in
Table 13-6: Summary of registers on page 13-10 and are described below.
Bit 0:
This bit controls the Data Terminal Ready (NDTR) output. When bit is set to
a logic 1, the NDTR output is forced to a logic 0. When bit 0 is reset to a logic
0, the NDTR output is forced to a logic 1.
Note: The NDTR output of the UART may be applied to an EIA inverting
line driver (such as the DS1488) to obtain the proper polarity input at the
succeeding MODEM or data set.
Bit 1:
This bit controls the Request to Send (NRTS) output. Bit 1 affects the NRTS
output in a manner identical to that described above for bit 0.
Bit 2:
Not used
Bit 3:
Not used
Bit 4:
This bit provides a local loopback feature for diagnostic testing of the UART.
When bit 4 is set to logic 1, the following occur: the transmitter Serial Output
(SOUT) is set to the Marking (logic 1) state; the receiver Serial Input (SIN)
is disconnected; the output of the Transmitter Shift Register is “looped back”
into the Receiver Shift Register input; the four MODEM Control inputs
(NCTS, NDSR, NDCD and NRI) are disconnected; and the two MODEM
Control outputs (NDTR and NRTS) are internally connected to the four
MODEM Control inputs, and the MODEM Control output pins are forced to
their inactive state (HIGH). On the diagnostic mode, data that is transmitted
is immediately received. This feature allows the processor to verify the
transmit- and received-data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully
operational. Their sources are external to the part. The MODEM Control
interrupts are also operational, but the interrupts sources are now the lower
four bits of the MODEM Control Register instead of the four MODEM
Control inputs. The interrupts are still controlled by the Interrupt Enable
Register.
Bit 5–7: These bits are permanently set to logic 0.
MODEM Status Register
This register provides the current state of the control lines from the MODEM (or peripheral
device) to the CPU. In addition to this current-state information, four bits of the MODEM Status
Register provide change information. These bits are set to a logic 1 whenever a control input
from the MODEM change state. They are reset to logic 0 whenever the CPU reads the MODEM
Status Register.
GMS30C7201 Data Sheet
13-17