GMS30C7201 Datasheet, PDF (200/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
The status registers contain bits which signal CRC, overrun, underrun, framing, and receiver
abort errors as well as the transmit buffer service request, receive buffer service request, and end
of frame conditions. Each of these hardware detected events signal an interrupt request to the
interrupt controller. The status registers also contains flags for transmitter busy, receiver
synchronized, receive buffer not empty, and transmit buffer not full (no interrupt generated).
12.9.1 FIr Status Register 0
FIr status register 0 (FISR0) contains bits which signal the transmit buffer service request,
receive buffer service request, receiver abort, transmit buffer underrun, framing error, and the
end/error in receive buffer condition. Each of these hardware detected events signal an interrupt
request to the interrupt controller.
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called
flags. Status bits are referred to as “sticky” (once set by hardware, must be cleared by software).
Writing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set
and cleared by hardware, writes have no effect. Additionally some bits which cause interrupts
have corresponding mask bits in the control registers and are indicated in the section headings
below.
End/Error in buffer Status (EIF) (read/write, non-maskable interrupt)
The end/error in buffer status bit (EIF) is set when any tag bits (32 through 36) are set in the
receive buffer. When EIF is set an interrupt is signalled and DMA requests to empty the receive
buffer are disabled until EIF is cleared
Transmit Underrun Status (TUR) (read/write, maskable interrupt)
The transmit underrun status bit (TUR) is set when the transmit logic attempts to fetch data from
the transmit buffer after it has been completely emptied. When an underrun occurs, the
transmitter takes one of two actions. When the transmit underrun select bit is clear (TUS=0) the
transmitter ends the frame by shifting out the CRC which is calculated continuously on outgoing
data, followed by a stop flag and SIP pulse. When TUS=1, the transmitter is forced to transmit
an abort and continues to transmit symbols containing all zeros (0000) until valid data is again
available within the buffer. Once data resides within the bottom entry of the transmit buffer, a
new data frame is initiated by transmitting sixteen preambles and a start flag followed by the
transmission of data from the buffer. When the TUR bit is set an interrupt request is made unless
it is masked. When TUS=0 the interrupt is masked, when TUS=1 it is enabled. Note that
underruns are not generated when the FIr transmitter is first enabled and is in the idle state
(continuously transmits flags).
Receiver Abort Status (RAB) (read/write, non-maskable interrupt)
The receiver abort status bit (RAB) is set when an abort is detected during receipt of an
incoming frame. An abort is signalled when two or more symbols which do not contain any
pulses (0000) or symbols containing 0011, 1001, 1010, or 0101(invalid symbols which are not
contained within the stop flag) are detected after a valid start flag has been detected but before
a complete stop flag has been received (i.e. an incorrect chip in the stop flag generates an abort
as well). When an abort is received, the EOF tag is set in the buffer entry which corresponds to
the last piece of data which was received before the frame was aborted. The receiver then enters
hunt mode, searching for the preamble.
Transmit buffer Service Request Flag (TFS) (read-only, maskable interrupt)
The transmit buffer service request flag (TFS) is a read-only bit which is set when the transmit
buffer is not full and requires service. When the TFS bit is set, an interrupt request is made
unless the transmit buffer interrupt request mask (TIM) bit is cleared. The state of TFS is also
sent to the DMA controller, and may be used to signal a DMA service request. Note that TIM
has no effect on the generation of the DMA service request. After the DMA or CPU fills the
buffer, the TFS flag (and the service request and/or interrupt) is automatically cleared.
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GMS30C7201 Data Sheet