GMS30C7201 Datasheet, PDF (48/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Memory Map
6.1 Introduction
There are five main memory map divisions, outlined in Table 6-1: Top-level address map.
Base Address
0Mbyte
64Mbytes
128Mbytes
192Mbytes
256Mbytes
320Mbytes
384Mbytes
512Mbytes
576Mbytes
640Mbytes
704Mbytes
768Mbytes
832Mbytes
896Mbytes
960Mbytes
1024Mbytes
1040Mbytes
1056Mbytes
1072Mbytes
1088Mbytes
1104Mbytes
1120Mbytes
1136Mbytes
1152Mbytes
2048Mbytes
Note:
Size
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
128Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
64Mbytes
16Mbytes
16Mbytes
16Mbytes
16Mbytes
16Mbytes
16Mbytes
16Mbytes
16Mbytes
896Mbytes
336Kbytes
Description
ROM chip select 0
ROM chip select 1
ROM chip select 2
ROM chip select 3
ROM chip select 4
ROM chip select 5
Reserved
PCMCIA card 1Attribute memory
PCMCIA card 1Common memory
PCMCIA card 1I/O or Secondary Common memory
Reserved
PCMCIA card 2 Attribute memory
PCMCIA card 2 Common memory
PCMCIA card 2 I/O or Secondary Common memory
Reserved
SDRAM chip select 0
SDRAM chip select 1
SDRAM chip select 2
SDRAM chip select 3
SDRAM mode register chip 0
SDRAM mode register chip 1
SDRAM mode register chip 2
SDRAM mode register chip 3
Reserved
Peripherals
Table 6-1: Top-level address map
The ROM has an address space of 384Mbytes which is split equally between six external ROM
chip selects.
PCMCIA 0 and 1 have three contiguous 64Mbyte pages.
The 64Mbyte address space at the top of the 256Mbyte allocated for each PCMCIA card is
reserved.
There is a maximum of 64Mbytes of SDRAM. The mode registers in the SDRAM are
programmed by reading from the 64Mbyte address space immediately above the SDRAM.
6-2
GMS30C7201 Data Sheet