GMS30C7201 Datasheet, PDF (211/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Device Controller
The Device Controller contains a state machine that understands the USB protocol. The (SIE)
provides the Device Controller with the type of packet, address value, endpoint value, and data
stream for each incoming packet. The Device Controller then checks to see if the packet is
targeted to the device by comparing the address/endpoint values with internal registers that were
loaded with address and endpoint values during the USB enumeration process. Assuming the
address/endpoint is a match, the Device Controller then interprets the packet. Data is passed on
to the endpoint for all packets except SETUP packets, which are handled specially. Data toggle
bits (DATA0 and DATA1 as defined by the USB spec) are maintained by the Device Controller.
For IN data packets (device to host) the Device Controller sends either the maximum number
of bytes in a packet or the number of bytes available from the endpoint. All packets are
acknowledged as per the spec. For SETUP packets, the incoming data is extracted into the
relevant internal fields, and then the appropriate action is carried out. Table 12-36: Supported
Setup Requests lists the types of setup operations that are supported.
Setup Request
Get Status
Clear Feature
Set Feature
Set Address
Get Descriptor
Set Descriptor
Get Configuration
Set Configuration
Get Interface
Set Interface
Synch Frame
Value Supported
0
Device, Interface, Endpoint
1
Endpoints Only
3
Not supported
5
Device
6
Device
7
Not supported
8
Device
9
Device
10
Not supported
11
Not supported
12
Not supported
Table 12-36: Supported Setup Requests
Start of Frame
The Start of Frame logic generates a pulse whenever either the incoming Start of Frame (SOF)
packet arrives or approximately 1 ms after it the last one arrived. This allows an isochronous
endpoint to stay in sync even if the SOF packet has been garbled.
12.10.4Endpoint FIFOs (Rx,Tx)
Each endpoint FIFO has the specific number of FIFO depth according to data transfer rate. In
case of maximum packet size for bulk transfer is 32 bytes that is supported in USBD. Each FIFO
generates dataready signals (means FIFO not full or FIFO not empty) to AMBA I/F and causes
AMBA I/F to produce DMAC request signals. It contains the control logic for transferring 4
bytes at a read/write strobe generated by AMBA to obtain better efficiency of AMBA bus.
12.10.5AMBA Interface
The AMBA I/F performs the decoding APB signal, generating DMA request signal, comparing
with endpoint FIFO status signal. And it also prevents FIFOs overrun/underrun error. There are
5 registers
GMS30C7201 Data Sheet
12-57