GMS30C7201 Datasheet, PDF (169/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
DMA Channel Priority
When the DMAC receives simultaneous transfer requests, it selects a channel according or a
predetermined priority order. The priority order is selected by the priority order select bits,
PRMD0 and PRMD1, in the DMA operation register.
DMA bus mode
Burst mode
Once the bus mastership is obtained, the transfer is performed continuously until the transfer
end condition is satisfied. however, when the nDMREQ pin is driven high, the bus passes to the
other bus master after current cycle ends. DMA request is nDMREQ level detection.
nDMREQ
CPU
CPU
DMA
DMA
DMA
DMA
CPU
Exception mode
In the exception mode, the bus mastership is given to another bus master after a one-transfer-
unit
DMA transfer.
The DMA request should be disabled by I/O device module.
DMA request is nDMREQ level detection.
nDMREQ
CPU
DMA
CPU
CPU
DMA
CPU
CPU
GMS30C7201 Data Sheet
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