GMS30C7201 Datasheet, PDF (241/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Desired
Baud Rate
50
-
110
-
-
300
-
1200
-
-
2400
-
4800
-
9600
19200
38400
57600
115200
3.6864Mhz
Decimal
Divisor
Used to
Generate 16
x Clock
Percent
Error
Difference
Between
Desired and
Actual
4608
-
-
-
2094
0.026
-
-
-
-
768
-
-
-
192
-
-
-
-
-
96
-
-
-
48
-
-
-
24
-
12
-
6
-
4
2
Table 13-8: Baud rates
Line Status Register
This register provides status information to the CPU concerning the data transfer. Table 13-6:
Summary of registers on page 13-10 shows the contents of the Line Status Register. Details on
each bit follow.
Bit 0:
This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1
whenever a complete incoming character has been received and transferred
into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic 0 by
reading all of the data in the Receiver Buffer Register or the FIFO.
GMS30C7201 Data Sheet
13-13