GMS30C7201 Datasheet, PDF (60/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
FCLK (ARM Processor and SDRAM controller clock)
Derived from PLL3 whose Frequency is controllable between 49.7664 MHz and 82.944 MHz.
Frequency of operation is set using a 6 bit register.
There are two methods for updating frequency, depending upon the state of bit 6 of the Clock
Control register ClkCtl (see ClkCtl register on page 7-11). If bit 6 is set, then any data written
to bits [5:0] of the ClkCtl register are immediately transferred to the pins of PLL3, thus causing
the loop to unlock and to mute FCLK. This is only a safe mode of operation if PLL3 frequency
and mark-space ratio is guaranteed to be within limits immediately after the Lock Detect signal
has become active. If bit 6 is NOT set, then the GMS30C7201 must enter DEEP sleep mode
before bits [5:0] of the Clock Control register are transferred to PLL3.
To switch between the two frequencies when bit 6 is not set:
• Software writes the new value into the ClkCtl register
• Set a Real Time Clock Alarm to wake the GMS30C7201 in 2 seconds
• Enter DEEP SLEEP Mode by writing to the PMUMode Register
• The GMS30C7201 will power up with PLL3 running at the new frequency
BCLK
BusClock, which is generated by the PMU by dividing FCLK by 2.
VCLK
Clock for the LCD and VGA video controller. Frequency selectable between 31.5MHz or
40MHz. The VCLK PLL is disabled when on BnRES is active or when the PMU is put into
DEEP SLEEP mode. On exit from either of these conditions, the VCLK PLL must be re-enabled
by software.
Changing Frequency:
1 Software must first disable the VCLK pll, by writing a ‘0’ to the PLL1Enable bit of the
ClkCtl register.
2 Write the new value to the PLL1Freq bit.
3 Re-enable the VCLK pll by writing 1 to the PLL1Enable bit.
CCLK
Clock for the IR comms and the USB. Nominally 48MHz. The CCLK PLL is disabled when
BnRES active or when the PMU is put into DEEP SLEEP mode. On exit from either of these
conditions, the CCLK PLL must be re-enabled by software.
PMU state machine
The state machine handles the transition between the power management states described
below. The CPU can write to the PMU mode registers (which is what would typically happen
when a user switches off the device) and the state machine will proceed to the commanded state.
7-4
GMS30C7201 Data Sheet