GMS30C7201 Datasheet, PDF (142/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
Bit
27
31-28
Name
Skip4
-
Description
Skip every fourth clock HIGH period to allow color passive LCD to run with shared VGA DMA.
Reserved
Table 11-5: LCD Controller Bit Fields (Continued)
11.6.8 Clocks Per Line (CPL)
This is the actual number of clocks output to the LCD panel each line, minus one. This must be
programmed, in addition to the PPL field in the LCD Timing 0 Register. The number of clocks
per line is the number of pixels per line divided by either one, four, eight or two-and-two-thirds
for TFT mode, mono 4-bit mode, mono 8-bit, or color STN mode respectively.
11.6.9 Bypass Pixel Clock Divider
Setting this bit allows an undivided LCD clock to be output on LCD. This bit should only be set
for TFT mode.
11.6.10Skip every fourth clock pulse (Skip 4)
Set this bit to “1” when running a color passive LCD with simultaneous VGA display in Shared
DMA, Slave mode. This produces an irregular clock to the LCD, where every fourth clock pulse
is suppressed (the clock stays LOW for one clock period). This is necessary because two-and-
two-third pixels per clock, which are sent to the LCD, is not an integer multiple. This means that
three clocks will be output every four clock periods. If PCD is zero, then eight pixels will be
output every eight LcdClk periods, since the LCD CP clock will be half the frequency of
LcdClk.
11-14
GMS30C7201 Data Sheet