GMS30C7201 Datasheet, PDF (135/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.3 Video Control register
This register contains control bits for both the VGA and the LCD controllers. The reason that
both VGA and LCD control bits are in the same register is to allow the simultaneous enabling
of LCD and VGA when sharing DMA data.
11.3.1 LCD Power Control
LCD displays require that the LCD is running before power is applied. For this reason, the
LCD’s power on control is not set to “1” unless both LcdEn and LcdPwr are set to “1”. Note
that most LCD displays require the LcdEn must be set to “1” approximately 20ms before
LcdPwr is set to “1” for powering up. Likewise, LcdPwr is set to “0” 20ms before LcdEn is
set to “0” for powering down.
Bit
0
2-1
3
4
7-5
8
10-9
11
12
15-13
Name
LcdEn
LcdBpp
LcdBW
LcdTFT
-
VgaEn
VgaBpp
ShareDMA
BGR
-
Description
LCD Controller Enable
0 - LCD controller disabled
1 - LCD controller enabled
LCD Bits Per Pixel
00 - 4bpp
01 - 8bpp
10 - 16bpp
11 - Reserved
LCD Monochrome
0 - Color operation enabled
1 - Monochrome operation only enabled
LCD TFT
0 - Passive or STN display operation enabled
1 - Active or TFT display operation enabled
Reserved
VGA Controller Enable
0 - VGA controller disabled
1 - VGA controller enabled
VGA bits per pixel
00 - 4bpp
01 - 8bpp
10 - 16bpp
11 - Reserved
Share DMA Data
If this bit is set, the DMA data streams for LCD and VGA are shared. The
request is only generated when there is space for data in both FIFOs (both
FIFO requests should be programmed to 8 words). The LCD timing
generator should be slaved off the VGA timing generator, with the clock
source set as the VGA clock.
0 - RGB normal video output for both LCD and VGA
1 - BGR red and blue swapped for both LCD and VGA
Reserved
Table 11-2: Video control register VideoControl
GMS30C7201 Data Sheet
11-7