GMS30C7201 Datasheet, PDF (272/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Channel Control Register (Timer2)
bit 0
1 = start count
0 = stop count
bit 1
1 = count repeat mode
bit 2
1 = reset Counter Register
bit[7:3] Reserved
Channel Test Register
This register is for chip test purposes only. All bits should
be 0 during normal operation.
bit 0
“1” clock of 5th bit (bit 4) is from clock
source
bit 1
“1” clock of 9th bit (bit 8) is from clock
source
bit 2
“1” clock of 13th bit (bit 12) is from clock
source
bit 3
“1” clock of 17th bit (bit 16) is from clock
source
bit 4
“1” clock of 21st bit (bit 20) is from clock
source
bit 5
“1” clock of 25th bit (bit 24) is from clock
source
bit 6
“1” clock of 29th bit (bit 28) is from clock
source
bit 7
Reserved
Top Control Register
bit 0
Timer 0 interrupt enable/disable
bit 1
Timer 1 interrupt enable/disable
bit 2
Timer 2 interrupt enable/disable
1 = interrupt enable
0 = interrupt disable. If all three bits are 0,
then INTTIMER is always 0.
bit 3
Timer enable
1 = enable (normal mode)
0 = disable (lower power mode - default)
bit 4
enable 64-bit counter
1 = enable. When this bit is set, the period of
Timer 1 is used as the clock source of Timer
2.
In this mode, the period of Timer 2 is the
product of the base register value of Timer 1
and the base register value of Timer 2.
0 = disable
bit[7:5] Reserved
13-44
GMS30C7201 Data Sheet