GMS30C7201 Datasheet, PDF (226/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Notes
Bit
Initial Value
Description
12
0
When only TICdac mode, this bit can be programmed:
0 - interrupt not request
1 - interrupt request
11
0
When only TICdac mode, this bit can be programmed:
0 - DMA not request
1 - DMA request
10
0
When only TICdac mode, this bit can be programmed:
0 - DAC operation run
1 - DAC operation stop
9
0
When only TICdac mode, this bit can be programmed:
0 - DLEFT LOW
1 - DLEFT HIGH
8
0
When only TICdac mode, this bit can be programmed:
0 - DRIGHT LOW
1 - DRIGHT HIGH
7–0 0
SD signal.
When only TICdac mode, this bit can be programmed.
Table 12-47: Test Output Register (STOR)—programmable register (Continued)
(1) Soundclk: this is an internal signal used as a reference clock source to play the sound data.
(2) Dapulse: this is an internal signal used to make the DAC channel select signal.
Test Input Register (STIR)—read-only register
This register is for monitoring the unit status and the signals to DAC in both normal and Ticdac
mode.
Bit
Initial Value
Description
14
0
Soundclk state. This bit indicates the state of Soundclk signal.
13
0
Dapulse state. This bit indicates the state of Dapulse signal.
12
0
This bit is set by INT signal in Ticdac and normal mode:
0 - interrupt not request
1 - interrupt request
11
0
This bit is set by DRQ signal in Ticdac and normal mode.
0 - DMA not request
1 - DMA request
10
0
This bit is set by IOSTOP signal in Ticdac and normal mode.
0 - DAC operation run
1 - DAC operation stop
9
0
This bit is set by DLEFT signal in Ticdac and normal mode.
0 - DLEFT LOW
1 - DLEFT HIGH
Table 12-48: Test Input Register(STIR)—Read-only Register
12-72
GMS30C7201 Data Sheet