GMS30C7201 Datasheet, PDF (175/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Address: 0h 80011004
IrCon
Read/Write
Bit
7 65 4 3 2 1 0
AME TIM RIM RXE TXE TUS BRD -
Reset 0 0 0 0 0 0 0 ?
Figure 12-3: Location of bits within Ir Control Register
Bit
Name
0
1
BRD
2
TUS
3
TXE
4
RXE
5
RIM
6
TIM
7
AME
Description
Unused
MIr bit rate select
0 - MIr data rate is 0.576 Mbit/s
1- Mir data rate is 1.152 MBit/s
Transmit buffer Underrun Select
0 - Transmit buffer underrun causes CRC, stop flag, and SIP to be transmitted, and masks
interrupt generation (TUR ignored)
1 - Transmit buffer underrun causes an abort to be transmitted, and generates an interrupt
(state of TUR sent to interrupt controller)
Transmit Enable
0 - Ir transmit logic disabled
1 - Ir transmit logic enabled
Receive Enable
0 - Ir receive logic disabled
1 - Ir receive logic enabled
Receive buffer Interrupt Mask
0 - Receive buffer half-full or more condition does not generate an interrupt (RFS bit ignored)
1 - Receive buffer half-full or more condition generates an interrupt (state of RFS sent to
interrupt controller)
Transmit buffer Interrupt Mask
0 - Transmit buffer half-full or less condition does not generate an interrupt (TFS bit ignored)
1 - Transmit buffer half-full or less condition generates an interrupt (state of TFS sent to
interrupt controller)
Address Match Enable
0 - Disable receiver address match function, store data from all incoming frames in receive
buffer
1 - Enable receiver address match function, do not buffer data unless address recognized or
incoming address contains all ones (0hFF)
Table 12-25: Ir Control Register
GMS30C7201 Data Sheet
12-21