GMS30C7201 Datasheet, PDF (187/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
preset to all ones before reception/transmission of each frame. Note that the CRC is transmitted
and received starting with its MSB and ending with its LSB. The CRC uses the four-term
polynomial:
CRC(x)= (X¹⁶ + X¹² + X⁵ + 1)
Baud Rate Generation
The baud or bit rate is derived by dividing down the 48MHz clock generated by the on-chip
PLL. The clock is first divided down by 10 and five-twelfths, then either 1 (BRD=1) or 2
(BRD=0), and then by a fixed value of four, generating the transmit clock for 1.152Mb/s and
0.576Mb/s data rates, respectively. The receive clock is generated by the receiver Digital Phase
Locked Loop (DPLL). The DPLL uses a sample clock that is undivided. A sample rate counter
(incremented at the sample clock rate) is used to generate a receive clock at the nominal data
rate (sample clock divided by 41 and two-thirds). The sample rate counter is reset on the
detection of each positive-going data transition (indicating the RZI encoding of a ‘0’) to ensure
that synchronization with the incoming data stream is maintained.
Receive Operation
Once the MIr receiver is enabled it enters hunt mode, searching the incoming data stream for
the flag (01111110). The flag serves to achieve bit synchronization, denotes the beginning of a
frame, and delineates the boundaries of individual bytes of data. The end of the flag denotes the
beginning of the address byte. Once the flag is found, the receiver is synchronized to incoming
data and hunt mode is exited.
After each bit is decoded, a serial shifter is used to receive the incoming data a byte at a time.
Once the flag is recognized, each subsequent byte of data is decoded and placed within a
two-byte temporary buffer. A temporary buffer is used to prevent the CRC from being placed
within the receive buffer. When the temporary buffer is filled, data values are pushed out one
by one to the receive buffer. The first byte of a frame is the address. If receiver address matching
is enabled, the received address is compared to the address programmed in the address match
value field in a control register. If the two values are equal or if the incoming address contains
all ones, all subsequent data bytes including the address byte are stored in the receive buffer. If
the values do not match, the receive logic does not store any data in the receive buffer, ignores
the remainder of the frame and begins to search for the stop flag. The second byte of the frame
can contain an optional control field that must be decoded in software (There is no hardware
support within the MIr). Use of a control byte is determined by the user.
When the receive buffer is filled, a DMA request is signalled. If the data is not removed soon
enough and the buffer is completely filled, an overrun error is generated when the receive logic
attempts to place additional data into the full buffer. Once the buffer is full, all subsequent
received data are lost while the buffer contents remain intact.
Frames can contain any amount of data in multiples of 8-bits. Although the MIr protocol does
not limit frame size, in practice they tend to be implemented in numbers ranging from hundreds
to a couple of thousand bytes.
The receive logic continuously searches for the stop flag at the end of the frame. Once it is
recognized, the last byte that was placed within the receive buffer is flagged as the last byte of
the frame, and the two bytes remaining within the temporary buffer are removed and used as the
16-bit CRC value for the frame. Instead of placing this in the receive buffer, the receive logic
compares it to the CRC-CCITT value which is continuously calculated using the incoming data
stream. If they do not match, the last byte that was placed within the receive buffer is also
flagged with a CRC error. The CRC value is not placed in the receive buffer.
The MIr protocol permits back to back frames to be received. When this occurs, three flags
separate back to back frames.
Most commercial IrDA transceivers can generate an abort (7 to 13 ones) when their transmit
buffer underruns. The receive logic contains a counter that increments each time a one is
decoded before entering the serial shifter, and is reset any time a zero is decoded. When seven
GMS30C7201 Data Sheet
12-33