GMS30C7201 Datasheet, PDF (159/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Name
BD[31:0]
AREQ
AGNT
Granted
BERROR
BLAST
BLOCK
BPROT[1:0]
BSIZE[1:0]
BTRAN[1:0]
BWAIT
Type
InOut
Out
In
Out
InOut
InOut
Out
Out
Out
Out
InOut
Source/
Destination
ASB bus
Arbiter
Arbiter
APB
ASB bus
ASB bus
ASB bus
ASB bus
ASB bus
ASB bus
ASB bus
BWRITE
DSEL
nDMREQ[2:0]
Chan[1:0]
TransendINT
DMATest
InOut
In
In
Out
Out
Out
ASB bus
Decoder
I/O device
APB
CPU
Arbiter
Fast AMBA Peripherals
Description
This is part of the bidirectional system data bus.
Request signal for ASB Bus mastership.
Bus Grant signal from ASB arbiter.
This signal informs APB of the granted Bus state.
ASB error signal.
ASB break burst signal from Slave (SDRAM Controller).
ASB locked transfer signal
ASB master protection information.
ASB transaction size signal
ASB transaction type signal.
ASB wait transfer signal. Input for DMA cycle stretch.
Out for Register access.
ASB transfer direction signal
Register select signal
DMA transfer request signal from the I/O device
DMA channel select signal to APB
DMA transfer end interrupt signal to CPU
This signal informs DMA Test mode during TIC test.
Table 12-1: ASB Signal Description (Continued)
GMS30C7201 Data Sheet
12-5