GMS30C7201 Datasheet, PDF (64/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
7.5 PMU Registers
The base address of the PMU registers (PMUBase) is defined in Table 6-2: Peripherals base
addresses on page 6-3. The offsets from PMUBase of the PMU registers are described in
Table 7-1: PMU register map.
Address
PMUBase + 0x00
PMUBase + 0x08
PMUBase + 0x10
PMUBase + 0x18
PMUBase + 0x20
PMUBase + 0x28
PMUBase + 0x30
PMUBase + 0x38
Read location
PMUMode
Piccolo Enable
ID
Bus Retract
ResetStatus
ClkCtl
Debounce Counters (test only)
General Purpose Test
Write location
PMUMode
Piccolo Enable
Reserved
Bus Retract
ResetStatusClear
ClkCtl
Debounce test register
General Purpose Test
Table 7-1: PMU register map
PMU mode register
This read/write register is written to by the CPU to change mode from RUN mode or SLOW
mode into a different mode. The encoding is shown below, in Table 7-2: Mode entry encodings.
Obviously the register can only be read and written to in RUN mode or SLOW mode, since these
are the only modes in which the processor can access these registers. Therefore, the processor
will never be able to read values for modes other than mode 0x00 and mode 0x 01. Other values
may be read by a test controller so long as clocks are enabled with bit 8 of the DbCtr register.
See Table 7-12: DbCtr Register Bit 8 on page 7-13.
Note
PMUMode[2:0] register value
0x04
0x01
0x00
0x02
0x03
0x07
PMUMode[3]
PMU Mode
Initialisation mode
RUN mode
SLOW mode
IDLE mode
SLEEP mode
DEEP SLEEP mode
Writing a ‘1’ to this bit allows PMU to exit
DEEP SLEEP mode when pins PMBATOK
and PMADAPOK are both low.Writing a ‘0’
to this bit prevents the PMU from leaving
DEEP SLEEP mode when PMBATOK and
PMADAPOK are both low
Table 7-2: Mode entry encodings
All other values in the above table are undefined.
7-8
GMS30C7201 Data Sheet