GMS30C7201 Datasheet, PDF (345/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

15.5.2 SDRAM interface signals
SCLK
Electrical Characteristics
SD[15:0] (read)
T_sdsu
SD[15:0] (write)
nSRAS, nSCAS,
nSWE, nSCS[3:0],
SCKE[3:0], SA[13:0],
SDQMU, SDQML
T_sdih
T_sd
T_sdoh
T_sd
T_sdz
T_sden
T_sdoh
Figure 15-3: SDRAM interface timing
Symbol
Tsdsu
Tsdih
Tsd
Tsdoh
Tsdz
Tsden
Parameter
Min
Max
SDRAM data in setup time to SCLKr
0
-
SDRAM data in hold from SCLKr
2
-
Signal delay from SCLKr
2
7
SDRAM data output hold time from SCLKr
2
-
SDRAM data bus disable time from SCLKr
2
11
SDRAM data bus enable time from SCLKr
2
9
Table 15-9: Provisional SDRAM interface AC parameters (units ns)
Timing values are derived from simulations using 0pF signal loading. Actual circuit output
delays should be calculated by adding manufacturers signal load de-rating delay values.
GMS30C7201 Data Sheet
15-9