GMS30C7201 Datasheet, PDF (189/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.8.2 MIr Register Definitions
The MIr uses the control and data registers described in the previous section. These are shared
with the FIr interface and can only be used with the MIr when the MIr is selected using the
IrEnable register. In addition to the shared registers there are two status registers specific to the
MIr.
The status registers contain bits that signal CRC, overrun, underrun and receiver abort errors as
well as the transmit buffer service request, receive buffer service request and end of frame
conditions. Detection of end of frame, underrun and receiver abort errors signal interrupt
requests to the interrupt controller. The status registers also contains flags for transmitter busy,
receiver synchronized, receive buffer not empty, transmit buffer not full and receive transition
detect (No interrupt is generated).
12.8.3 MIr Status Register 0
MIr status register 0 (MISR0) contains bits that signal the transmit buffer service request,
receive buffer service request, receiver abort, transmit buffer underrun and the end/error in
receive buffer condition. Detection of receiver abort, transmit buffer underrun and the end/error
in receive buffer condition signal an interrupt request to the interrupt controller.
Bits that cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called
flags. Status bits are referred to as “sticky” (once set by hardware, they must be cleared by
software). Writing a one to a sticky status bit clears it, writing a zero has no effect. Read-only
flags are set and cleared by hardware, writes have no effect.
End/Error in buffer Status (EIF)(read-only)
The end/error in buffer flag (EIF) is a read-only bit that is set when any tag bits (32-36) are set
in either entry of the receive buffer, and is cleared when no error bits are set within the buffer.
When EIF is set an interrupt is signalled and DMA requests to empty the receive buffer are
disabled until EIF is cleared. Once all set tag bits are cleared from the receive buffer, EIF is
automatically cleared, which in turn clears the interrupt and re-enables the receive buffer DMA
request.
Transmit Underrun Status (TUR) (read/write)
The transmit underrun status bit (TUR) is set when the transmit logic attempts to fetch data from
the transmit buffer while it and the tail register are empty. When an underrun occurs, the
transmitter takes one of the following two actions. When the transmit underrun select bit is clear
(TUS=0) the transmitter ends the frame by shifting out the CRC which is calculated
continuously on outgoing data, followed by a flag. When TUS=1, the transmitter is forced to
transmit an abort and continues to transmit ones until valid data is again available within the
buffer. Once data resides in the transmit buffer, a new data frame is initiated by transmitting an
SIP and a start flag followed by the transmission of data from the buffer. When the TUR bit is
set, an interrupt request is made. Note that underruns are not generated when the MIr transmitter
is first enabled and is in the idle state (continuously transmits flags).
Receiver Abort Status (RAB)(read/write)
The receiver abort status bit (RAB) is set for two different cases:
• when an abort is detected during receipt of an incoming frame
• if the stop flag is not received on a byte boundary.
An abort is signalled when seven or more consecutive ones are detected in the incoming data
stream. It is also generated when the end flag is received and it is not on a byte boundary, which
indicates that the address, control and data fields did not add up to an even multiple of 8-bits.
When an abort is detected, the current data byte within the serial shifter is discarded, the least
recent byte (the oldest of the two bytes) of data in the temporary buffer is moved to the receive
GMS30C7201 Data Sheet
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