GMS30C7201 Datasheet, PDF (123/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PCMCIA Interface
10.3 Functional Description
10.3.1 Socket 1 and Socket 2 Access
To reduce the external pin count, common data and address signals are used for socket 1 and
socket2 with two additional control signals (CaDRV, CbDRV). This scheme dramatically
reduces the external pin count with some burdens of board level system design. An external
buffer selects the exact path. Address and Data paths uses EBI for the same reason above. And
to meet the wide range of address setup time and hold time of various PCMCIA card according
to the access time deference, some software control method is used. Access Timing Control
Register is used for this scheme. The access time of PCMCIA Card is relatively very slow when
compared to the host system operating clock speed. So, the controller must provide some signal
e.g, BWAIT, to inform the host that current access has not finished. Three wait conditions
guarantee normal operation. See Figure 10-4: Memory Read Cycle With Wait:
1 default wait until PCMCIA Card drives the wait
2 PCMCIA card driven wait
3 additional wait to meet the long address hold time - AND-ORed to inform the host of
the state of current access
Addr
A25:A1
-REG
A0
-CE1
-CE2
-OE
-WE
-WAIT
Data
1
Setup
Cycle Time
D7:D0(odd byte)
2
Command
3
Hold
GMS30C7201 Data Sheet
Figure 10-4: Memory Read Cycle With Wait
10-23