GMS30C7201 Datasheet, PDF (72/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
An Externally generated Warm RESET
Note
Figure 7-5: An Externally Generated Warm RESET
• nRESET is driven to ‘0’ by external hardware. The nRESET input is filtered by a de-
bounce circuit. Note that this means that nRESET must remain low for a minimum of
40ms. BnRES (the on-chip reset signal) becomes active as soon as nRESET is low,
and high once the de-bounced nRESET goes high once more. BnRES disables PLL1
and PLL2. The CPU may read the RESET register, which will return 0x106:
Bit
Interpretation
bit 1 set:
PLL1 has been ‘unlocked’
bit 2 set:
PLL2 has been ‘unlocked’
bit 8 set:
A RESET event has occurred.
Table 7-15: Bit Settings for a Warm RESET within RESET STATUS register
The internal chip reset, BnRES, remains active for 20ms after an externally generated
nRESET. External devices should not assume that the GMS30C7201 is in an active state during
this period.
7-16
GMS30C7201 Data Sheet