GMS30C7201 Datasheet, PDF (74/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
8.1 SDRAM Controller Specification
The system RAM resource is provided by SDRAM, on an interface that is run at the
GMS30C7201’s core clock frequency. Between 2 and 64Mbytes of external SDRAM are
supported by one to four external devices. To reduce power consumption, each SDRAM device
has its own Clock Enable (CKE), so each device may individually be placed in low power mode
when idle. The SDRAMs are powered down into self-refresh mode when the whole system is
placed in standby mode.
Internal to the GMS30C7201, the SDRAM controller arbitrates between access requests from
the Main AMBA bus, and a custom Video bus.
The best use of an SDRAM is made when data is streamed in sequence, and future access
requests can be predicted. It is in the nature of video data to be accessed in sequence at regular
intervals; however, SDRAM accesses from the ARM are a lot less predictable. The SDRAM
controller makes use of access predictability to maximize the use of memory interface
bandwidth by having simultaneous access to both the LCD and VGA address buses. Video
accesses to the SDRAM occur in fixed-burst lengths of 16 words, ARM and DMA controller
accesses occur in a fixed-burst length of four words. If the requested accesses are shorter than
four words, then the extra data is ignored.
8-2
GMS30C7201 Data Sheet