GMS30C7201 Datasheet, PDF (202/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Bit
Name
3
TFS
4
RFS
5
FRE
7–6 WST
Description
Transmit buffer Service Request (read-only)
0 - Transmit buffer is full or the transmitter disabled
1 - Transmit buffer is not full and the transmitter is enabled. A DMA service request is
signalled, interrupt request is signalled if not masked (if TIM=1)
Receive buffer Service Request (read-only)
0 - Receive buffer is empty or receiver disabled
1 - Receive buffer is not empty and receiver operation is enabled, DMA service request
signalled, interrupt request signalled if not masked (if RIM=1)
Framing Error
0 - No framing errors encountered in the receipt of this data
1 - Framing error occurred, preamble followed by something other than another preamble or
start flag, request interrupt
Width Status
00 - All four bytes in receive buffer are valid
01 - Least significant byte valid only
10 - Least significant two bytes valid only
11 - Least significant three bytes valid only
Table 12-32: FIr Status Register 0 (Continued)
FIr Status Register 1
FIr status register 1 (FISR1) contains flags that indicate when the receiver is synchronized, the
transmitter is active, that the transmit buffer is not full, that the receive buffer is not empty, and
when an end of frame, CRC error, or underrun error has occurred. All bits within FISR1 are
read-only and non-interrupting.
Receiver Synchronized Flag (RSY)
(read-only, non-interrupting)
The receiver synchronized (RSY) flag is a read-only bit which is set when the receiver is
synchronized with the incoming data stream, and is cleared when the receiver logic is in hunt
mode (looking for the preamble to achieve byte and frame synchronization), or the receiver is
disabled (RXE=0). This bit does not request an interrupt.
Transmitter Busy Flag (TBY)
(read-only, non-interrupting)
The transmitter busy (TBY) flag is a read-only bit which is set when the transmitter is actively
transmitting a frame (address, control, data, CRC, start or stop flag), and is cleared when the
transmitter is idle (transmitting preambles), or the transmitter is disabled (TXE=0). This bit does
not request an interrupt.
End of Frame Flag (EOF)
(read-only, non-interrupting)
The end of frame flag (EOF) is set when the last byte of data within a frame (including aborted
frames) resides within the receive buffer.
The receive buffer contains five tag bits (32 - 36) which are not directly readable. The 32nd bit
is set at the top of the buffer whenever the last byte within a frame is moved from the receive
serial shifter to the receive buffer. Each time a data value is transferred to the buffer, the state of
the tag bit is moved to the EOF bit in the status register. Whenever EOF, EIF is set within FISR0,
an interrupt is signalled, and the receive buffer DMA request is disabled.
CRC Error Status (CRE)
(read-only, non-interrupting)
The CRC error flag (CRE) is set when the CRC value calculated by the receive logic does not
match the CRC value contained within the incoming serial data stream.
12-48
GMS30C7201 Data Sheet