GMS30C7201 Datasheet, PDF (167/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Bit 1 (MODSEL: Mode select bit)
MODSEL
0
1
Description
DMAC transfers data from memory to I/O buffer
DMAC transfers data from I/O buffer to memory
Table 12-15: Bit 1
Bit 2 (MASK: The mask bit of transfer end interrupt for receive buffer)
MASK
0
1
Description
Interrupt request is not generated even if data transfer ends by the
specified count (initial value)
Interrupt request is generated if data transfer ends by the specified
count
Table 12-16: Bit 2
Channel Control Register 2(CCR2)
This register is the channel control register of the Universal Serial Bus interface controller.
Bit 0 (DMEN: Enables channel 2 operation)
DMEN
0
1
Description
Disables channel 2 operation (initial value)
Enables channel 2 operation
Bit 1 (MODSEL: Mode select bit)
Table 12-17: Bit 0
MODSEL
0
1
Description
DMAC transfers data from memory to I/O buffer
DMAC transfers data from I/O buffer to memory
Table 12-18: Bit 1
Bit 2 (MASK: The mask bit of transfer end interrupt for receive buffer)
MASK
0
1
Description
Interrupt request is not generated even if data transfer ends by the
specified count (initial value)
Interrupt request is generated if data transfer ends by the specified
count
Table 12-19: Bit 2
GMS30C7201 Data Sheet
12-13