GMS30C7201 Datasheet, PDF (278/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.8.3 Register map
25 The CP reads the SPISR register in the SPI-MMC block and disable start signal (reset
XCH bit). In other words, CP writes the SPICR register.
26 After CP take last data from RX FIFO, CP de-asserts CS signal.
Table 13-35: SPI-MMC block register map shows a register map of the SPI-MMC block.
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
Register Name
SPICR
SPISR
XCHCOUNTER
TXdatabuffer
RXdatabuffer
Testregister1
Testregister2
ResetReg
Dummy
TIC
Type
R/W
R
R/W
W
R
R
R
R/W
R
R
Value in reset
0100000
00000000
00000000000
000000000
000000000
0”
Does not exist
Description
SPI control register
SPI status register
Number of exchange data
TX data buffer (8*8 bits)
RX data buffer (8*8 bits)
SPI test register1
SPI test register2
SPI reset register
Test clock generation
TIC register
Table 13-35: SPI-MMC block register map
6
5
DATA RATE
CS
4
xchmode
3
TestMode
2
LOOP
1
SPIEN
0
XCH
SPICR register
DATA RATE
These bits select the baud rate of the SPICLK based on divisions of
the system clock. The master clock for the SPIMMC is PCLK.The
bits are encoded as:
0 = bypass
1 = Divide by 2
13-50
GMS30C7201 Data Sheet