GMS30C7201 Datasheet, PDF (70/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
RESET SEQUENCES
Power on RESET.
Figure 7-3: A Cold RESET event
In the event of removal and re-application of all power to the GMS30C7201, the following
sequence may be typical:
• nPOR input is active. All internal registers are reset to their default values. The PMU
drives nRESETout LOW to reset any off-chip peripheral devices.
• BnRES becomes active on exit from the nPOR condition. Clocks are enabled
temporarily to allow synchronous resets to operate.
• The default frequency of FCLK on exit from nPOR will be 49.7664MHz.
• When FCLK is stable, the CPU clock is released. If the CPU were to read the RESET/
Status register at this time, it will return 0x10f:
Bit
Meaning
bit 0 set:
Power On Reset event has occurred
bit 1 set:
PLL1 has been ‘unlocked’
bit 2 set:
PLL2 has been ‘unlocked’
bit 3 set:
PLL3 has been ‘unlocked’
Table 7-13: Bit Settings for a Cold RESET Event within RESET STATUS register
• The CPU may write 0x10f to the RESET register to clear these flag bits.
• The CPU writes 0x20 to the clock control register, which will set a FCLK speed of
58.9824MHz. The new clock frequency, however, is not adopted until the PMU has
entered and left DEEP SLEEP mode.
• The CPU sets a RTC timer alarm to expire in approximately 2 seconds
• The CPU sets DEEP SLEEP into the PMU Mode Register
7-14
GMS30C7201 Data Sheet