GMS30C7201 Datasheet, PDF (293/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.10.2Signal Description
The RTC module is connected to the APB. Table 13-50: APB signal descriptions describes the
APB signals used and produced. Table 13-51: Specific block signal descriptions shows the
non-AMBA signals from the block.
Name
nPOR
PA[4:2]
PD[31:0]
PSTB
PWRITE
PSEL
PCLK
Type
In
In
Source/
Destination
External
APB Bridge
InOut
In
APB Peripherals,
BD bus
APB Bridge
In
APB Bridge
In
APB Bridge
In
APB Clock Gen
Description
Power on reset.
This is part of the peripheral address bus, which is used by this
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes HIGH and remain valid
after PSTB goes LOW.
This is the bidirectional peripheral data bus. The data bus is driven by
this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus. The
falling edge of PSTB is coincident with the falling edge of BCLK
(ASB system clock).
When HIGH, this signal indicates a write to a peripheral and when
LOW, a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes HIGH and remains valid after PSTB
goes LOW.
When HIGH, this signal indicates the RTC module has been selected
by the APB bridge. This selection is a decode of the system address bus
(ASB). For more details, see AMBA Peripheral Bus Controller (ARM
DDI 0044).
The slow APB clock used to re-synchronize data transfers between the
32768Hz clock and the APB.
Table 13-50: APB signal descriptions
Name
CLK32KHZ
SRTCEV
URTCEV
CLK4K
Type
In
Out
Out
Out
Source/
Destination
Clock generator
APB peripheral
(Interrupt Controller)
APB peripheral
APB peripheral
Description
32768Hz clock input. This is the signal that clocks the counter
during normal operation.
Interrupt signal to the Interrupt module. When HIGH, this
signal indicates a valid comparison between the counter value
and the match register. It also indicates 1Hz interval with
enable bit in control register.
When HIGH, this signal indicates a valid comparison between
the counter value and the match register. This signal is used to
wake up the GM30C7201 when it is asleep.
This signal is used in the power management block.
Table 13-51: Specific block signal descriptions
GMS30C7201 Data Sheet
13-65