GMS30C7201 Datasheet, PDF (95/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Static Memory Interface
9.3 Functional Description
The Static Memory Controller has six main functions:
• memory bank select
• access sequencing
• wait states generation
• burst read control
• byte lane write control
These are described below.
9.3.1 Memory bank select
The chip select signal generation is controlled by BA[28:26], DSEL and BWRITE. Refer to
Table 9-2: Static memory bank select coding.
DSEL
BA[28:26] nCS[5:0] Memory Configuration
0
XXX
111111
not selected
1
000
111110
nCS0 configuration
1
001
111101
nCS1 configuration
1
010
111011
nCS2 configuration
1
011
110111
nCS3 configuration
1
100
101111
nCS4 configuration
1
101
011111
nCS5 configuration
Table 9-2: Static memory bank select coding
9.3.2
Access sequencing
Bank configuration also determines the width of the external memory devices. When the
external memory bus is narrower than the transfer initiated from the current master, the internal
transfer will take several external bus transfers to complete.
9.3.3
Wait states generation
The Static Memory Controller supports wait states for read and write accesses. This is
configurable between one and 16 wait states for standard memory access, and zero and 15 wait
states for burst mode.
The Static Memory Controller also allows transfers to be extended indefinitely. This is done by
asserting EXPRDY LOW. To hold the current transfer, EXPRDY must be asserted on the
falling edge of BCLK before the last cycle of the accesses. The transfer cannot complete until
EXPRDY is HIGH for at least one cycle.
9.3.4 Burst read control
This supports sequential access burst reads of up to four consecutive locations in 8-, 16- or 32-
bit memories.
GMS30C7201 Data Sheet
9-5