GMS30C7201 Datasheet, PDF (266/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.6 Interrupt Controller
The interrupt controller has the following features:
• a status register
• selection of the output path (IRQ or FIQ for each input)
• enabling the interrupt
The interrupt controller provides a simple software interface to the interrupt system.
In an ARM system, two levels of interrupt are available:
• FIQ (Fast Interrupt Request) for fast, low-latency interrupt handling
• IRQ (Interrupt Request) for more general interrupts
Ideally, in an ARM system, only a single FIQ source would be in use at any particular time. This
provides a true low-latency interrupt, because a single source ensures that the interrupt service
routine may be executed directly without the need to determine the source of the interrupt. It
also reduces the interrupt latency because the extra banked registers, which are available for FIQ
interrupts, may be used to maximum efficiency by preventing the need for a context save.
The interrupt controller provides a bit position for each different interrupt source. Bit positions
are defined for a software programmed interrupt.
Any interrupt source can be programmed as a source to FIQ or IRQ interrupt.
All interrupt source inputs must be active HIGH and level sensitive.
No hardware priority scheme nor any form of interrupt vectoring is provided, because these
functions can be provided in software. Any interrupt source may be masked.
13.6.1 In/Out signals
Signal
PD[23:0]
PA[4:2]
PSEL
PSTB
PWRITE
BnRES
INT[23:0]
nIRQ
nFIQ
Type
Description
InOut
Data Bus
In
Address Bus
In
Chip Select
In
Strobe Signal
In
nRead/Write
In
Reset Signal
In
Interrupt Request Inputs
Out
Interrupt Request to CPU
Out
Fast Interrupt Request to CPU
Table 13-29: Interrupt Controller in/out signals
13-38
GMS30C7201 Data Sheet