GMS30C7201 Datasheet, PDF (138/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.5 LCD Timing 1 Register
LCD Timing 1 Register (LcdTiming1) contains four bit-fields that are used to control LCD
vertical timing parameters.
11.5.1 Lines Per Screen (LPS)
The Lines Per Screen (LPS) bit-field is used to specify the number of lines or rows per LCD
panel being controlled. LPS is a 10-bit value which represents between 1–1024 Lines Per
Screen. The register is programmed with the number of lines per screen minus 1.
11.5.2 Vertical Sync Pulse Width (VSW)
The 6-bit vertical sync pulse width (VSW) field is used to specify the pulse width of the vertical
synchronization pulse in active mode, or is used to add extra dummy line clock delays between
frames in passive mode. The register is programmed with the number of lines of VSync minus
one.
11.5.3 Vertical Front Porch (VFP)
The 8-bit Vertical Front Porch (VFP) field is used to specify the number of line clocks to insert
at the end of each frame. Once a complete frame of pixels is transmitted to the LCD display, the
value in VFP is used to count the number of line clock periods to wait. After the count has
elapsed the VSync (LcdFP) signal is pulsed in active mode, or extra line clocks are inserted as
specified by the VSW bit-field in passive mode. VFP generates from 0–255 line clock
cycles.This should be zero for passive display modes, unless synchronizing to the VGA to share
data.
11.5.4 Vertical Back Porch (VBP)
The 8-bit Vertical Back Porch (VBP) field is used to specify the number of line clocks to insert
at the beginning of each frame. The VBP count starts just after the VSync signal for the previous
frame has been negated for active mode, or the extra line clocks have been inserted as specified
by the VSW bit-field in passive mode. After this has occurred, the value in VBP is used to count
the number of line clock periods to insert before starting to output pixels in the next frame. VBP
generates from 0–255 extra line clock cycles. This should be programmed to zero in passive
mode, unless sensing LCD to VGA to share DMA data.
Bit
9-0
15-10
23-16
31-24
Name
LPS
VSW
VFP
VBP
Description
Lines Per Screen
Number of lines per screen. Program to number of lines required minus 1.
Vertical Sync Pulse Width
Number of VSync lines. Should be small for passive LCD, but should be
long enough to re-program the video palette under interrupt control, without
writing the video palette at the same time as video is being displayed.
Program to the number of lines required minus one.
Vertical Front Porch
Number of inactive lines at the end of frame, before VSync period. Program
to zero on passive displays.
Vertical Back Porch
Number of inactive lines at the start of a frame, after VSync period.
Program to zero on passive displays.
Table 11-4: Lcd Timing Register 1
11-10
GMS30C7201 Data Sheet