GMS30C7201 Datasheet, PDF (81/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
8.4.2 Refresh Timer
Address: SDRAM register base address + 4
A 16-bit read/write register that is programmed with the number of BCLK ticks that should be
counted between SDRAM refresh cycles.
For example, for the common refresh period of 16µs, and a BCLK frequency of 50MHz, the
following value should be programmed into it:
16x10^-6 * 50x10⁶ = 800
The refresh timer defaults to a value of 128, which for a 16µs refresh period assumes a worst
case (ie. slowest) clock rate of:
128
16x10^-6
= 8 MHz
The refresh register should be written to as early as possible in the system start-up procedure,
and in the first few cycles if the system clock is less than 8MHz.
8.4.3
Write buffer flush timer
Address: SDRAM register base address + 8
A 3-bit read/write register that selects the time-out value for flushing the quad word merging
write buffer. The times are given in the following table.
Timer value
BCLK ticks between time-outs
0
Time-out disabled
1
2
2
4
3
8
4
16
5
32
6
64
7
128
Table 8-7: Write buffer: flush time-out table
GMS30C7201 Data Sheet
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