GMS30C7201 Datasheet, PDF (168/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
DMA Test Register
The DMA Test Register is a 32 bits read/write register that tests the DMA Master. Initial value:
0x00.
DMA Operation Register (DMAOR)
The DMA Operation Register is a 32 bits read/write register that controls the DMA Master. Bit
0 (DMAEN: Enables or disables DMA transfers on all channels).
DMAEN
0
1
Description
Disable DMA transfer on all channels (initial value)
Enable DMA transfer on all channels
Table 12-20: DMA Operation Register (DMAOR)
Bit1 (PRMD0–1): Select the priority level between channels when there are transfer requests
for multiple channels simultaneously.
PRMD1
0
0
1
1
PRMD0
0
1
0
1
Description
Ch1 > Ch2 > Ch0 (initial value)
Ch1 > Ch0 > Ch2
Ch2 > Ch1 > Ch0
Ch0 > Ch1 > Ch2
Table 12-21: Bit 1 (PRMD0-1)
12.2.13DMAC Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order. If the transfer end conditions are satisfied, it ends the
transfer.
12.2.14DMA Transfer Flow
After the DMA address register (ADR, ASR), DMA transfer number register (TNR), DMA
channel control register (CCR), and DMA operation register (DMAOR) are set, the DMAC
transfers data according to the following procedure.
• See if the DMEN bit of CCR and the DMAEN of DMAOR are enabled.
• When a transfer request comes and transfer condition is enabled, the DMAC transfers
data according to bus size, address mode and bus mode.
• When the specified number of transfer have been competed (TNR = count value), the
transfer ends normally. If the MASK bit of the CCR is set to 1 at this time, the DMA
transfer end interrupt is sent to the CPU.
12-14
GMS30C7201 Data Sheet