GMS30C7201 Datasheet, PDF (199/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
When the transmit buffer is emptied, an interrupt and/or DMA service request is signalled. If
new data is not supplied quickly enough, and the transmit logic attempts to take additional data
from the empty buffer, one of two actions can be taken as programmed by the user. An underrun
can either signal the normal completion of a frame or an unexpected termination of a frame in
progress.
When normal frame completion is selected and an underrun occurs, the transmit logic transmits
the 32-bit CRC value calculated during the transmission of all data within the frame (including
the address and control bytes), followed by the stop flag to denote the end of the frame. The
transmitter then continuously transmits preambles until data is once again available within the
buffer. Once data is available, the transmitter begins transmission of the next frame.
When unexpected frame termination is selected and an underrun occurs, the transmit logic
outputs an abort and interrupts the CPU. An abort continues to be transmitted until data is once
again available in the transmit buffer. The FIr then transmits 16 preambles, a start flag, and starts
the new frame. The remote receiver may choose to ignore the abort and continue to receive data,
or to signal the FIr to retry transmission of the aborted frame.
At the end of each frame transmitted, the FIr outputs a pulse called the serial infrared interaction
pulse (SIP). A SIP is required at least every 500ms to keep slower speed devices (115.2Kbps
and slower) from colliding with the higher speed transmission. The SIP simulates a start bit
which causes all low speed devices to stay off the bus for at least another 500ms. Transmission
of the SIP pulse causes the transmit pin to be forced high for a duration of 1.625us and low for
7.375us (total SIP period = 9.0us). After the 9.0us elapses, the preamble is then transmitted
continuously to indicate to the remote receiver that the FIr’s transmitter is in the idle state. The
preamble continues to be transmitted until new data is available within the transmit buffer, or
the FIr’s transmitter is disabled. Note that it is the responsibility of the user to ensure that a
frame completes once every 500ms such that a SIP pulse is produced keeping all low speed
devices from interrupting transmission. Because most IrDA compatible devices produce a SIP
after each frame transmitted, the user may only need to ensure that a frame is either transmitted
or received by the FIr every 500ms. Note that frame length does not represent a significant
portion of the 500ms time frame in which a SIP must be produced. At 4.0Mbps, the longest
frame allowed is 16,568 bits, which takes just over 4ms to transmit. Also note that the FIr issues
a SIP when the transmitter is first enabled, to ensure all low speed devices are silenced before
transmitting it’s first frame.
If the user disables the FIr’s transmitter during operation, transmission of the current data byte
is stopped immediately, the serial shifter and transmit buffer are cleared and all clocks used by
the transmit logic are automatically shut off to conserve power.
CPU and DMA Register Access Sizes
Bit positioning, byte ordering, and addressing of the FIr is describes in terms of little endian
ordering. All FIr control and status registers are 8 bits wide and are located in the least
significant byte of individual words. Data transfers are up to 32 bits wide. If the DMA controller
is used to service the transmit and/or receive buffers, the user must ensure the DMA is properly
configured to perform single word-wide accesses.
DMA burst mode access is not supported.
FIr Register Definitions
The Fir uses the control and data registers described in 12.3 Medium and Fast Infrared Module
on page 12-17. In addition there are two status registers specific to the FIr
The status registers contain bits which signal CRC, overrun, underrun, framing, and receiver
abort errors as well as the transmit buffer service request, receive buffer service request, and end
of frame conditions. Each of these hardware detected events signal an interrupt request to the
interrupt controller. The status registers also contain flags for transmitter busy, receiver
synchronized, receive buffer not empty, and transmit buffer not full (no interrupt generated).
GMS30C7201 Data Sheet
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