GMS30C7201 Datasheet, PDF (182/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.6 Receiving Data
Any data error or reception of the end of frame will cause an interrupt to be generated which
may be masked with the IrCon.RIM bit (Receive Interrupt Mask).
12.6.1 Initialization
Address Matching
To use Address Match filtering, set the local 8-bit address in the Address Match Value Register,
and set the Address Match Enable bit in the IrCon register.
Set up DMA for Receive
1 Store the destination address (word aligned) for incoming data in DMAADDR1.
2 Store the maximum buffer size in words in DMATNR1.
3 Set DMACCR1.MODSEL (selects transfer from IO to memory)
4 Set DMACCR1.MASK (enables end of transfer interrupt)
5 Set DMACCR1.DMEN1 (enables DMA transfer)
6 Ensure that the master enable bit in the DMAC Operation Register is set.
Enable Ir Receive
Set the Receive Enable bit (RXE) in IrEnable
12.6.2 End of Frame
End of Frame Interrupt
An interrupt is generated when a complete frame has been received or when an error in the
received data has been detected. To detect if the interrupt is due to reception of a complete frame
or due to an error condition, different status registers are used depending on whether MIr or FIr
is in operation. In this description, SR0 and SR1 are referred to. In MIr mode, these would be
IrMSR0 and IrMSR1. In FIr these would be IrFSR0 and IrFSR1.
Note
Bit positions for flags in IrMSR1 and IrFSR1 are not identical.
Completing Received Data Transfer
If SR0.RFS (Receive buffer service request flag) is set, then there is valid data in the Ir FIFO
which has not been moved by DMA into the external buffer. SR0.WST0 & SR0.WST1 indicate
how many valid bytes there are in the top entry of the FIFO. If both bits are zero then there are
four valid bytes in the top entry of the FIFO.
To append the data to the data already transferred by DMA, the address of the next word in the
DMA buffer must be calculated. The address can be found by subtracting the current value in
DMATNR1 (transfer count) from the original value to get the number of words already
transferred. This value can then be added to DMAADR1 to give the destination for the word
read from IrDATA. In general, there will be 1 to 4 bytes in the receive FIFO, but in exceptional
circumstances it is possible that there is another entry in the Ir FIFO, so SR0.RFS should be
checked and if necessary the next entry (one to four bytes, indicated by SR0.WST0 &
SR0.WST0) appended to the input buffer.
12-28
GMS30C7201 Data Sheet