GMS30C7201 Datasheet, PDF (261/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Name
PBOE[7:0]
Type
Out
Source/
Destination
PADS
PC[7:0]
Out PADS
EPC[7:0] In
PADS
PCOE[7:0] Out PADS
PD[7:0]
Out PADS
EPD[7:0] In
PADS
PDOE[7:0] Out PADS
Description
Port B output enable (active LOW). Values written on PBDDR register are put onto
these lines.
Port C output driver. Values written on PCDR register are put onto these lines and driven
out to the port C pins if the corresponding data direction bits are set HIGH (PCDDR
register).
Port C input driver. It reflects the external state of the port. This information is obtained
when reading the PCDR register.
Port C output enable (active LOW). Values written on PCDDR register are put onto
these lines.
Port D output driver. Values written on PDDR register are put onto these lines and driven
out to the port D pins if the corresponding data direction bits are set LOW (PDDDR
register).
Port D input driver. It reflects the external state of the port. This information is obtained
when reading the PDDR register.
Port D output enable (active LOW). Values written on PDDDR register are put onto
these lines.
Table 13-25: Specific block signal descriptions (Continued)
13.5.3 Functional description
All pins are defined as input during reset (BnRES LOW).
For each port there is a Data Register and a Data Direction Register. On reads, the Data Register
contains the current status of correspondent port pins, whether they are configured as input or
output. Writing to a Data Register only affects the pins that are configured as outputs.
All PIO input pins can be used as interrupt source with enabled interrupt mask register bit. These
interrupt sources can be selected as active HIGH/LOW, EDGE/LEVEL trigger mode.
Bits[5:0] of port B and bit[3:0] of port D are multiplexed with other functions and regarded as
multi-function pins. In order to use these multi-function pins as PIO pins, the Multi-function Pin
Selection register (PMPS) bit should be set.
13.5.4 Programmer’s model
PIO registers
The following user registers are provided:
P[A,B,C,D]DR
Data Register. Values written to this 8-bit read/write register will be output
on port [A,B,C,D] pins if the corresponding data direction bits are set Low
(port output). Values read from this register reflect the external state of port
[A,B,C,D] not necessarily the value written to it. All bits are cleared by a
system reset.
P[A,B,C,D]DDR Port [A,B,C,D] Data Direction Register. Bits set in this 8-bit read/write
register will select the corresponding pin in port [A,B,C,D] to become an
input, clearing a bit sets the pin to output. All bits are set by a system reset.
All PIO signals can be used as interrupt sources according to the settings. Each port has the
following registers and interrupt signals to interrupt controller. Interrupt controller receives
active HIGH, level mode interrupt sources only. But PIO block can receive not only active
HIGH or active LOW, but also level or edge mode signals. Then interprets and sends interrupt
GMS30C7201 Data Sheet
13-33