GMS30C7201 Datasheet, PDF (137/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.4 LCD Timing 0 Register
LCD Timing 0 Register (LcdTiming0) contains four bit-fields that are used to control horizontal
LCD timing. See 11.6.2 Pixel Clock Divider (PCD) on page 11-12 for a description of the terms
“PixelClock” and “LcdClk”
11.4.1 Pixels-per-line (PPL)
The pixels-per-line (PPL) bit-field is used to specify the number of pixels in each line or row on
the screen. PPL is a 6-bit value that represents between 16–1024 pixels-per-line. PPL is used to
count the correct number of pixel clocks that must occur before the line clock can be pulsed.
Program the value required divided by 16, minus 1.
11.4.2 Horizontal Sync Pulse Width (HSW)
The 6-bit horizontal sync pulse width (HSW) field is used to specify the pulse width of the line
clock in passive mode, or horizontal synchronization pulse in active mode. (Program the value
required minus 1.)
11.4.3 Horizontal Front Porch (HFP)
The 8-bit Horizontal Front Porch (HFP) field is used to specify the number of pixel clock
periods to insert at the end of each line or row of pixels before pulsing the line clock pin. Once
a complete line of pixels is transmitted to the LCD driver, the value in HFP is used to count the
number of pixel clocks to wait before pulsing the line clock. HFP generates a wait period
ranging from 1–256 pixel clock cycles. (Program to value required minus one.)
11.4.4 Horizontal Back Porch (HBP)
The 8-bit Horizontal Back Porch (HBP) field is used to specify the number of pixel clock
periods to insert at the beginning of each line or row of pixels. After the line clock for the
previous line has been negated, the value in HBP is used to count the number of pixel clocks to
wait before starting to output the first set of pixels in the next line. HBP generates a wait period
ranging from 1–256 pixel clock cycles (Program to value required minus one.).
Bit
1-0
7-2
15-8
23-16
31-24
Name
-
PPL
HSW
HFP
HBP
Description
Reserved
Pixels-per-line
Number of pixels per line, divided by 16, minus 1
Horizontal Sync Pulse Width
Number of LcdClk clock periods to pulse the line clock at the end of each
line minus 1
Horizontal Front Porch
Number of LcdClk clock periods to add to the end of a line transmission
before line clock is asserted, minus 1
Horizontal Back Porch
Number of LcdClk clock periods to add to the beginning of a line
transmission before the first set of pixels is output to the display minus 1
Table 11-3: Lcd Timing Register 0
11.4.5 VGA Timing 0 Register
The VGA Timing 0 register has the same format as the LCD Timing 0 Register.
GMS30C7201 Data Sheet
11-9