GMS30C7201 Datasheet, PDF (239/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Register Address
2 Data Bit 2 Data Bit 2 Enable
Interrupt XMIT
Number of
receiver line ID Bit 1 FIFO reset stop bits
status
interrupt
3 Data Bit 3 Data Bit 3 Enable
modem
status
interrupt
Interrupt
ID Bit 2
(Note 2)
Parity
enable
4 Data Bit 4 Data Bit 4 0
0
Reserved Even parity Loop
select
5 Data Bit 5 Data Bit 5 0
0
Reserved Stick parity 0
6 Data Bit 6 Data Bit 6 0
7 Data Bit 7 Data Bit 7 0
FIFO
enabled
(Note 2)
FIFO
enabled
(Note 2)
RCVR
trigger
(LSB)
RCVR
trigger
(MSB)
Set break 0
Divisor
0
latch access
bit
Parity Error Trailing
Bit
(PE)
Edge Ring
Indicator
(TERI)
2
Bit
2
Bit
Framing
Error
(FE)
Deltas Data
Carrier
Detect
(DDCD)
Bit 3
Bit 3
Bit 11
Break
Interrupt
(BI)
Clear to
Bit
Send
(CTS)
4
Bit
4
Bit
Transmitter
holding
register
empty
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
Transmitter Ring
Bit
empty
Indicator
(TEMT)
(RI)
6
Bit
6
Bit
Error in
RCVR FIFO
(Note 2)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
Table 13-6: Summary of registers (Continued)
Notes
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the 16450 mode.
The system programmer may access any of the UART registers summarized in Table 13-3:
Register address on page 13-7 via the CPU. These registers control UART operation including
transmission and reception of data. Each register bit in the table has its name and reset state
shown.
Line Control Register
The system programmer specifies the format of the asynchronous data communications
exchange and set the Divisor Latch Access bit via the Line Control Register (LCR). The
programmer can also read the contents of the Line Control Register. The read capability
simplifies system programming and eliminates the need for separate storage in system memory
of the line characteristics. Table 13-6: Summary of registers on page 13-10 shows the contents
of the LCR. Details on each bit follow.
Bit 0 and 1: These two bits specify the number of bits in each transmitted and received
serial character. The encoding of bits 0 and 1 is as follows:
Bit 2:
Bit 1
Bit 0
Character Length
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Table 13-7: Line control register encoding
This bit specifies the number of Stop bits transmitted and received in each
serial character. If bit 2 is a logic 0, one Stop bit is generated in the transmitted
GMS30C7201 Data Sheet
13-11