GMS30C7201 Datasheet, PDF (206/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.10 Universal Serial Bus
This section describes the implementation-specific options of USB protocol for a device
controller. It is assumed that the user has a knowledge of the USB standard. This USB Device
Controller(USBD) is chapter 9(of USB specification) compliant, and supports standard device
requests issued by the host. The user should refer to the Universal Serial Bus Specification
revision 1.0 for a full understanding of the USB protocol and its operation. (The USB
specification 1.0 can be accessed via the world wide web at: http://www.usb.org). The USBD is
a universal serial bus device controller (slave, not hub or host controller) which supports three
endpoints and can operate half-duplex at a baud rate of 12 Mbps. Endpoint 0,by default is only
used to communicate control transactions to configure the USBD after it is reset or physically
connected to an active USB host or hub. Endpoint 0’s responsibilities include connection,
address assignment, endpoint configuration and bus numeration.
The USBD is configured by the connected host which can get a device descriptor stored in
USBD’s internal ROM via endpoint 0. The USBD uses two separate 32 x 8 bit FIFOs to buffer
receiving and transmitting data to/from the host. The FIFOs can be accessed by the DMAC
(Direct Memory Controller), with service requests being signaled when either FIFO is full/
empty. The external pins dedicated to this interface are UVPO, UVP, UVMO, UVM,
URCVIN, nUSBOE and USUSPEND.These signals should be connected to USB transceiver
such as PDIUSBP11 provided by Philip Semiconductor. Refer to data sheet PDIUSBP11). The
interface of the USBD and the CPU uses DMAC to reduce CPU load of transferring data from
external memory to USBD and from USBD to external memory. The CPU can also access the
USBD using Interrupt controller, by setting the control register appropriately. This section also
defines the interface of USBD and CPU. The USBD uses one dedicated DMA channel for
receiving and transmitting data, so the DMAC should be programmed into receiving channel
initially for both data transferring. If transferring data to USB host occurs (setting the control
register bit), that is, USB host issue IN Token, then DMAC should be programmed to
transmitting channel. After transmitting data, DMAC should be programmed to the receiving
channel again.
12.10.1Features
• Full universal serial bus specification 1.0 Compliance.
• Receiver and Transceiver have 32 bytes FIFO individually (this supports maximum
data packet size of bulk transfer).
• Internal automatic FIFO control logic. (According to FIFO’s status, the USBD
generates DMA service request signals to DMAC or Interrupt service request signals
to the CPU)
• Supports high-speed USB transfer (12Mbps).
• There are two endpoint of transmitter and receiver respectively, totally three endpoints
including endpoint 0 that has responsibility of the device configuration.
• CPU can access the internal USB configuration ROM storing the device descriptor for
Hand-held PC (HPC) by setting the predefined control register bit.
• USB protocol and device enumeration is performed by internal state-machine in the
USBD.
• The USBD only supports bulk transfer of 4 transfer type supported by USB for data
transfer.
• Endpoint FIFO (Tx, Rx) has the control logic preventing FIFO’s overrun and underrun
error.
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GMS30C7201 Data Sheet