GMS30C7201 Datasheet, PDF (68/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PMU & PLL
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2c
0x2D
other values
ClkCtl[6]: PLL3 Frequency
update
0
1
66.3552 MHz
68.1984 MHz
70.0416 MHz
71.8848 MHz
73.7280 MHz
75.5712 MHz
77.4144 MHz
79.2576 MHz
81.1008 MHz
82.9440 MHz
reserved
Function
PLL3 frequency control frequency is only updated when PMU exits
DEEP SLEEP mode (default)
PLL3 frequency control frequency is updated instantaneously
ClkCtl[7]: PLL3Mute
0
1
ClkCtl[8]: PLL1Freq
0
1
Function
PLL3 is muted when Lock detect = 0 (default)
PLL3 only muted after nPOR or nRESET. Subsequent unlock
condition does not mute the clock. Allows dynamic changes to the
clock frequency without halting execution. Care: this only will be
legal if PLL3 is under-damped (i.e. will not exhibit overshoot in its
lock behavior).
Function
PLL1 set to max. frequency = 31.5MHz
PLL1 set to min. frequency = 40MHz
ClkCtl[9]: PLL1Enable
Function
0
PLL1 disabled
1
PLL1 enabled. Output will be gated until PLL1 Lock Detect (LD) is
received
ClkCtl[10]: PLL2Enable
Function
0
PLL2 disabled
1
PLL2 enabled. Output will be gated until PLL2 Lock Detect (LD) is
received
IF BIT 6 is ‘0’
Table 7-8: ClkCtl Register
When the CPU writes to bits 5:0 of this register, these bits are stored in a temporary buffer,
which is not transferred to the PLL until the next time the PLL lock signal becomes inactive.
This means that for a new value to take effect, it is necessary for the device to enter DEEP
SLEEP mode first.
IF BIT 6 is ‘1’
7-12
GMS30C7201 Data Sheet