GMS30C7201 Datasheet, PDF (260/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.5.2 Signal description
The PIO module is connected to the APB bus. Table 13-24: Signal descriptions on page 13-32
describes the APB signals used and produced. Table 13-25: Specific block signal descriptions
on page 13-32 shows the non-AMBA signals from the block.
Name
BnRES
PA[6:2]
PD[7:0]
PSTB
PWRITE
PSEL
Type
In
In
InOut
In
In
In
Source/
Destination
Description
Reset Controller
This signal indicates a power-on reset status of the bus (active LOW).
APB Bridge
This is part of the peripheral address bus, which is used by the peripheral
for decoding its own register accesses.
The addresses become valid before PSTB goes HIGH and remain valid
after PSTB goes LOW.
APB Peripherals, BD This is part of the bidirectional peripheral data bus. The data bus is driven
bus
by this block during read cycles (when PWRITE is LOW).
APB Bridge
This strobe signal is used to time all accesses on the peripheral bus. The
falling edge of PSTB is coincident with the falling edge of BCLK (ASB
system clock).
APB Bridge
When HIGH, this signal indicates a write to a peripheral and when LOW,
a read from a peripheral.
This signal has the same timing as the peripheral address bus. It becomes
valid before PSTB goes HIGH and remains valid after PSTB goes LOW.
APB Bridge
When HIGH, this signal indicates the PIO module has been selected by
the APB bridge. This selection is a decode of the system address bus
(ASB). For more details, see AMBA Peripheral Bus Controller (ARM
DDI 0044).
Table 13-24: Signal descriptions
Name
PA[7:0]
Type
Out
Source/
Destination
PADS
EPA[7:0] In
PADS
PAOE[7:0] Out PADS
PB[7:0]
Out PADS
EPB[7:0] In
PADS
Description
Port A output driver. Values written on PADR register are put onto these lines and driven
out to the port A pins if the corresponding data direction bits are set HIGH (PADDR
register).
Port A input driver. It reflects the external state of the port. This information is obtained
when reading the PADR register.
Port A output enable (active LOW). Values written on PADDR register are put onto
these lines.
Port B output driver. Values written on PBDR register are put onto these lines and driven
out to the port B pins if the corresponding data direction bits are set LOW (PBDDR
register).
Port B input driver. It reflects the external state of the port. This information is obtained
when reading the PBDR register.
Table 13-25: Specific block signal descriptions
13-32
GMS30C7201 Data Sheet