GMS30C7201 Datasheet, PDF (220/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Bit
7
6
5
4
3
2
1
RESERVED
MRX
0
MTX
Figure 12-31: DMAC request masking register
In CPU access mode, the DMAC request signal should be masked.
MTX: Mask FIFO empty DMAC request signal
When it is ‘1’, FIFO empty DMAC request signal is masked.
MRX: Mask FIFO full DMAC request signal.
When it is ‘1’, FIFO fullDMAC request signal is masked.
DMAC I/F
This field describes the interface of the DMAC and the USBD. The USBD (Rx/Tx buffer) trans-
mits and receives data from and to the DMAC based on the signal of the fast APB. That is, after
generating the DMA request signal, USBD expects the DMAC to produce PSELdmausb, PD,
PSTB and PWRITE that are the fast APB signals. With these signals, the FIFOs in Rx buffer
put data to PD and the FIFOs in Tx buffer get data from PD through the Quad Word Access.
Refer to the timing diagrams in 12.2.14 DMA Transfer Flow on page 12-14.
12.10.9Timing Values
Figure 12-4: Address match value field in the IrAmv Register on page 12-22 and Figure 12-
5: Bit locations within the Ir Data Register on page 12-23 give details of timing values.
12-66
GMS30C7201 Data Sheet