GMS30C7201 Datasheet, PDF (38/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Architecture Overview
3.5 Performance
ARM720T operation
The actual performance of the device will be highly application specific as well as dependent
on the speed of memory attached and the rate at which data is being transferred to the DMA
peripherals, in particular the LCD and VGA.
If a particular application or part of application is executing entirely from within the 720T cache
then the memory speed and peripheral DMA bandwidth may not have any affect at all. However
most applications will require access to either the static memory interface or the SDRAM
interface for its data structures and for instructions whenever there are cache misses. The cache
miss rate will have a large impact on the achievable performance, however it is impossible to
predict this for any general application.
It is possible though to give some indication of the potential performance of the device when
operating out of cache.
Run Mode operation (Cache on and operating at 60MHz, ASB clock at 30MHz):
Approximately 75K Dhrystones/s (~42.6 DMIPS)
Slow Mode operation (Cache on and operating at the ASB clock frequency of 30MHz):
Approximately 44K Dhrystones/s (~25 DMIPS)
* Both sets of figures assume two wait state memory external memory is available and no
peripheral DMA is active.
SP7 (Piccolo) operation
Once again it is not possible to generalize about the performance achievable on ARM720T
when the SP7 co-processor (Piccolo) is being used, it will depend entirely on the frequency with
which the ARM720T must transfer data to or from the SP7 co-processor which in turn is entirely
application dependent.
The performance of the ARM7TDSP processing element is best illustrated by its performance
for particular applications - it not possible to specify its performance in generalized MIPS terms.
SoftModem Performance
The following performance benchmarks have two columns. The first indicates the peak
processor requirement when averaged over two frames (triple frame buffering is used to ensure
no processor time overflow occurs). The peak occurs during the modem startup (training)
sequence. The average value represents the softmodem requirement once the startup sequence
has finished. All figures represent a system with data held in SDRAM, code held in 2 wait state
burst ROM, and 620x240 monochrome 4bpp LCD being displayed. The table below assumes
the CPU clock is running at 60MHz and the memory clock at 30MHz.
Modem standard
peak/MHz
average/MHz
V34bis with V42bis
54
42
v32bis
29
21
V17fax
14
14
Table 3-1: CPU clock cycles used for SoftModem
FFT performance
The following table illustrates the number of cycles it would take for an ARM720T and an
ARM720T with SP7 to perform a number of FFT points. All values assume perfect memory:
3-8
GMS30C7201 Data Sheet