GMS30C7201 Datasheet, PDF (177/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Receive Data FIFO
When IrData is read, the lower 32 bits of the bottom entry of the 37-bit two-stage receiver buffer
are accessed. Bits 33-36 are used as tags to indicate various conditions which occur during
reception of each piece of data. The tag bits are transferred down to the buffer along with the
data word which encountered the condition. Bit 32 of the buffer is automatically transferred to
the end of frame (EOF) flag, bit 33 to the CRC error (CRE) flag, and bit 34 to the receiver
overrun (ROR) flag, all within MIr/FIr status register 1. Bits 35 and 36 indicate whether the
received data word contains less than four valid data bytes, as occurs on the last word of a
received packet that is not an integer multiple of four bytes long. The user can read these flags
to determine if the value at the bottom of the buffer represents the last word within the frame
and/or encountered an error during reception. After checking the flags, the buffer value can then
be read.
The end/error in FIFO (EIF) status bit is set within status register 0 whenever one or more of the
tag bits (32-36) are set within the receive buffer. When EIF is set, an interrupt is generated and
the receive buffer DMA request is disabled so that the user can manually empty the buffer,
checking the end of frame, CRC error, and overrun error flags in status register 1 first before
removing each data value from the buffer. After the buffer is flushed, the user can re-enable
DMA servicing by clearing the EIF bit.
Transmit Data FIFO
When IrData is written, the transmit buffer is accessed. Data is removed from the buffer one
piece at a time by the transmit logic. Unlike the receive data FIFO, the transmit data FIFO may
only contain32-bit words. In order to transmit a frame containing a non-integer number of words
(multiple of four bytes) the Ir Data Tail Register must be used to store the final one, two or three
bytes of the frame (see 12.3.7 Ir Data Tail Register on page 12-24).
Figure 12-5: Bit locations within the Ir Data Register shows the bit locations corresponding
to the data field, end of frame bit, as well as the cyclical redundancy check and receiver overrun
error bits within the Ir Data Register. Note that both buffers are cleared when the ARM 7201 is
reset. Additionally the transmit buffer is cleared whenever the TXE bit is written with a zero in
IrCon, and the receive buffer is cleared whenever the RXE bit is written with a zero.
Address: 0h80011010
IrData
Read/Write
Bit
34 33 32 31 ... 5 4 3 2 1 0
WST1 WST0 ROR CRE EOF Bottom of receive buffer data
Reset 0
0
0 0 0 0 ... 0 0 0 0 0 0
Read Access
(Note: ROR, CRE, EOF are not read, but rather transferred to corresponding status bits in
MISR1/FISR1 each time a new data value is transferred to the top position in IrData)
Write Access
Bit 31 ... 5 4 3 2 1 0
Top of transmit buffer data
Reset 0 ... 0 0 0 0 0 0
GMS30C7201 Data Sheet
Figure 12-5: Bit locations within the Ir Data Register
12-23